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ST72411R
8-BIT MCU WITH SMARTCARD INTERFACE, LCD DRIVER, 8-BIT TIMER, SAFE RESET AND SUPPLY MONITORING
PRODUCT PREVIEW
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Memories - 4K Program memory (ROM/FLASH) with read-out protection - In-Situ Programming (remote ISP) for FLASH devices using Smartcard or standard I/O lines - 256-bytes RAM Clock, Reset and Supply Management - Power-on supply at Smartcard insertion - Low supply voltage detection for battery monitoring - Smart Card withdrawal detection - On-chip main clock source - 3 Power saving modes - Clock-out capability for synchronous and asynchronous Smartcards Smartcard Interface - Smart Card Supply Supervisor with: 3V or 5V voltage regulator and current overload protection 15 I/O Ports - 15 multifunctional bidirectional I/O lines with: external interrupt capability (2 vectors), 2 alternate function lines, 5 I/Os for ISO7816-3 Smartcard interface, 1 I/O for Smartcard withdrawal detection Display Driver - LCD driver with 32 segment outputs and 4 backplane outputs able to drive up to 32x4 LCD displays Timer - One 8-bit timer with: 9-bit prescaler, selectable input frequency with external clock input option and event output signal generation capability
TQFP64 14 x 14
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Instruction Set - 8-bit Data Manipulation - 63 Basic Instructions - 17 main Addressing Modes - 8 x 8 Unsigned Multiply Instruction - True Bit Manipulation Development Tools - Full hardware/software development package
Device Summary
Features Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Temperature Range Packages Development device ST72411R 4K 256 (64) Smart Card supply interface, LCD Driver, 8-bit Timer 4V to 6.6V (5.5V min. for 5V Smartcard power supply output) 3.58 MHz (7.16 MHz internal oscillator) 0C to +70C TQFP64 or Die Form ST72C411R
Rev. 1.4
January 2000 1/71
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Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Structural organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 In-Situ Programming (ISP) modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 11
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 LOW VOLTAGE DETECTOR AND SUPERVISOR (LVDS) . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 Low Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Open Power Supply Detection (OPSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Power Supply Supervisor (PSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 RESET SEQUENCE MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 MAIN CLOCK CONTROLLER SYSTEM (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 18 21 22 22 22
4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 I/O Port Interrupt Sensitivity Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Slow mode and VDD Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 8-BIT TIMER (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . . .. 5.3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 26 27 27 27 27 29 30 32 32 32 34 34 34 35 36 38
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5.4 32 X 4 LCD DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 41 41 41 43 44 44 46 46 46 46 47 48 50 50 51 51 51 51 51 52 52 53 5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Segment and Common signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Reference Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Display Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.7 LCD RAM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 SMARTCARD SUPPLY SUPERVISOR (SSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.3 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.4 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.5 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 FLASH Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 LCD ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 SMARTCARD SUPPLY SUPERVISOR ELECTRICAL CHARACTERISTICS . . . . . . . . . . 8 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 61 61 62 64 64 65 65
9.2 ADAPTOR / SOCKET PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . 70 10.1.1Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72411R devices are members of the ST7 microcontroller family. They are designed for Smartcard reader applications. All ST72411R family devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST72C411R devices feature single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Under software control, all devices can be placed in WAIT, SLOW, or HALT mode, reducing power Figure 1. Device Block Diagram consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
8-BIT CORE ALU RESET CONTROL
PROGRAM MEMORY (4K Bytes) RAM (256 Bytes)
OSC_SEL OSCIN INTEGR ATED 7.16 MHZ OSCILLATOR PB6:0 (7 bits) PORT B
LCD DRIVER + LCD RAM (32x4)
SEG31:0 (32 segments) COM3:0 (4 coms)
ADDRESS AND DATA BUS
PORT A PA7:0 (8 bits) 8-BIT TIMER
SC_PWR
SC SUPPLY SUPERVISOR (SSS)
VDD VSS VREF
LVDS
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1.2 PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout
SEG27 SEG26
SEG25
SEG24 SEG23
SEG22
SEG21 SEG20
SEG19 SEG18
SEG17 SEG16
SEG15
SEG14 SEG13
SEG28 SEG29 SEG30 SEG31 RESET ISP_SEL / OSC_SEL PA7 NC PA6 NC PA5 PA4 PA3 ISPCLK2 / PA2 ISPDATA2 / PA1 TIMIO / PA0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 2 46 3 45 4 44 5 43 6 42 7 EI0 1 8 9 EI0 10 11 12 13 EI0 14 41 40 39
SEG12
SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0
38 37 36 35 EI1 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDDA VDD VSSA NC VREF ISPCLK1 / (SC_CK) PB2 ISPDATA1 / (SC_DATA) PB1 (SC_RESET) PB0 SC_PWR PB5 (SC) PB4 (SC) PB3 VSS OSCIN NC PB6
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply Output level: SC = powered by VSC_PWR smartcard power, HS = high sink (on N-buffer only) Input level: C = CMOS : 0.3VDD/0.7V DD, SC = CMOS : 0.3VSC_PWR / 0.7VSC_PWR Port configuration capabilities: - Input:float = floating, wpu = weak pull-up, int = interrupt, wpd = weak pull-down - Output: OD = open drain, T = true open drain, PP = push-pull Note: Reset configuration of each pin is bold. Table 1. Device Pin Description
Pin n TQFP64 Type Pin Name Level Output Input Port Inpu t float wpu wpd int Output OD PP Main function (after reset) LCD Segment outputs Top priority non maskable interrupt. This pin acts as the Remote ISP mode and oscillator selection. C C C C C C C C X X X X X X X X EI0 EI0 EI0 EI0 EI0 EI0 EI0 EI0 X X X X X X X X X X X X X X X X Port A7 Port A6 Port A5 Port A4 Port A3 Port A2 Port A1 Port A0 ISP Clock line 2 ISP Data line 2 8-bit Timer I/O
Alternate function
1 ... 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
S28 ... S31 RESET OSC_SEL / ISP_SEL PA7 NC PA6 NC PA5 PA4 PA3 PA2 / ISPCLK2 PA1 / ISPDATA2 PA0 / TIMIO NC VREF PB6 PB5 PB4(SC) PB3(SC) PB2(SC_CK) / ISPCLK1 PB1(SC_DATA) / ISPDATA1 PB0(SC) SC_PWR VDDA VDD
1)
O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O C C X X X X X EI1 EI1 EI1 EI1 X EI1 X EI1 EI1 X X X X X X X X X X X X X X
Not Connected Not Connected
Not Connected Analog input for battery power monitoring Port B6 Port B5 Port B4 (Smartcard) Port B3 (Smartcard) Port B2 (Smartcard clock) Port B1 (Smartcard Data) Port B0 (Smartcard) Smartcard Regulated Supply Output Analog Power Supply Voltage Digital Main Supply Voltage ISP Clock line 1 ISP Data line 1
I/O SC SC I/O SC SC I/O SC SC I/O SC SC I/O SC SC O S S
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Pin n TQFP64 Type Pin Name
Level Output Input
Port Inpu t float wpu wpd int Output OD PP
Main function (after reset) Analog Ground Voltage Digital Ground Voltage
Alternate function
29 30 31 32
VSSA VSS OSCIN NC
S S I Not Connected O O
External main clock source LCD Common outputs LCD Segment outputs
33 ... 36 COM0 ... COM3 37 ... 64 SEG0 ... SEG27
Note: 1) There is no protection diode referenced to VDD on the VREF pad. If the microcontroller is not poweredon at the main VDD supply, it is possible to have no power consumption (other than leakage currents - see electrical parameters), while applying power to VREF.
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1.3 REGISTER & MEMORY MAP As shown in Figure 3, the MCU is capable of adressing 64K bytes of memories and I/O registers. The available memory locations consist of 64 bytes of register locations, up to 256 bytes of RAM, 16 bytes of LCD RAM and 4Kbytes of user Figure 3. Memory Map
0000h 003Fh 0040h
program memory. The RAM space includes up to 64 bytes for the stack from 0100h to 013Fh. The highest address bytes contain the user reset and interrupt vectors.
HW Registers (see Table 2) RAM (256 Bytes)
0040h
Short Addressing RAM (zero page)
00FFh 0100h
013Fh 0140h
LCD RAM (16 Bytes)
014Fh 0150h
Stack (64 Bytes)
013Fh
Reserved
EFFFh F000h
Program Memory (4K = 4096 Bytes)
FFDFh FFE0h FFFF h
Interrupt & Reset Vectors (see Table 4)
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h to 0030h 0031h 0032h 0033h 0034h to 003Fh TIMER PSCR TCR TSCR LCD SSS LCDCR SSSCR MISCR Port B PBDR PBDDR PBOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (25 Bytes) Miscellaneous Register Reserved Area (3 Bytes) LCD Control Register Smartcard Supply Supervisor Control Status Register Reserved Area (11 Bytes) Timer Prescaler register Timer Counter Register Timer Status Register Reserved Area (12 Bytes) FFh FFh 50h Read Only R/W R/W 00h 00h R/W R/W x0h R/W 00h 00h 00h R/W R/W R/W Reset Status 00h 00h 00h Remarks R/W R/W R/W
Port A
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1.4 FLASH PROGRAM MEMORY 1.4.1 Introduction Flash devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-bybyte basis. 1.4.2 Main features s Remote In-Situ Programming (ISP) mode s Up to 16 bytes programmed in the same cycle s MTP memory (Multiple Time Programmable) s Read-out memory protection against piracy 1.4.3 Structural organisation The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. The FLASH program memory is mapped in the upper part of the ST7 addressing space (F000hFFFFh) and includes the reset and interrupt user vector area. 1.4.4 In-Situ Programming (ISP) modes The FLASH program memory can be programmed using two Remote ISP modes. These ISP modes allow the contents of the ST7 program memory to be updated using a standard ST7 programming tool after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact. Examples of Remote ISP hardware interfaces to the standard ST7 programming tool are described below. For more details on ISP programming, refer to the ST7 Programming Specification. Remote ISP Overview The Remote ISP modes are initiated by a specific sequence on the dedicated ISPSEL pin. The Remote ISP is performed in three steps: - Selection of the RAM execution mode - Download of Remote ISP code in RAM - Execution of Remote ISP code in RAM to program the user program into the FLASH Remote ISP hardware configuration Remote ISP mode works using either the internal oscillator (no external clock is necessary), or an external square wave clock. The selection of the oscillator (internal or external) depends on the ISP_SEL pin during the rising edge of RESET pin ST72411 (see "MAIN CLOCK CONTROLLER SYSTEM (MCC)" on page 21). Two ISP modes exist: s ISP1: ISP signals mapped on smartcard I/O pins s ISP2: ISP signal mapped on general purpose I/O pins ISP1 Mode In ISP1 mode, it is possible to re-program the microcontroller using a ISO7816 smartcard connector as shown in Figure 3. This mode requires five signals (plus the SC_PWR signal if necessary) to be connected to the programming tool. These signals are: - RESET: device reset - VSS: device ground power supply - ISPCLK1: ISP output serial clock pin - ISPDATA1: ISP input serial data pin - ISPSEL: Remote ISP mode selection. This pin has an internal pulldown and must be left high impedance if the internal oscillator is selected. Otherwise an appropriate pull-up is needed (see Electrical Characteristics). Note: The RESET and ISPSEL pins are not part of the ISO7816 interface. Consequently, two additional contacts on the smartcard connector are necessary. Table 3. ISP1 (Smartcard) interface
SMARTC ARD FOR ISP
ISO7816 SMARTCARD CONNECTOR
VDD
ISPSEL RESET VSS
SC_PWR ISPCLK1 ISPDATA 1
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FLASH PROGRAM MEMORY (Cont'd) ISP2 Mode This mode requires five signals (plus the VDD signal if necessary) to be connected to the programming tool. These signals are: - RESET: device reset - VSS: device ground power supply - ISPCLK2: ISP output serial clock pin - ISPDATA2: ISP input serial data pin - ISPSEL: Remote ISP mode selection. This pin must be left high impedance (internal pull down on pin ISPSEL) if the internal oscillator is selected. Otherwise an appropriate pull-up is needed (see Electrical Characteristics). If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level. Figure 4 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description. Figure 4. Typical Remote ISP2 Interface
HE10 CONNECTOR TYPE TO PROGRAMMING TOOL
1
VDD
ISPSEL
VSS RESET
ST7
ISPCLK2 ISPDATA 2 4.7k
APPLICATION
1.5 Program Memory Read-out Protection The read-out protection is enabled through an option bit. For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is automatically erased.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES
s s s s s s s s
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
2.3 CPU REGISTERS The 6 CPU registers shown in Figure 13 are not present in the memory mapping and are accessed by specific instructions. Figure 5. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITIO N CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
ter it and reset by the IRET instruction at the end of the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware when you en-
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CENTRAL PROCESSING UNIT (Cont'd) STACK POINTER (SP) Read/Write Reset Value: 013Fh
15 0 7 0 0 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 6). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Figure 6. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 6. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 013Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 013Fh Stack Lower Address = 0100h
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3 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72411 microcontroller includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. Main Features s VDD Low Voltage Detection and Supervisor (LVDS) s Reset Sequence Manager s Main Clock Controller System (MCC) 3.1 LOW VOLTAGE SUPERVISOR (LVDS) DETECTOR AND Provided the minimum VDD value (guaranteed for the oscillator frequency) is below VIT-, the MCU can only be in one of two modes: - Under full software control - In static safe reset In this condition, secure operation is always ensured for the application without the need for external reset hardware. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. 3.1.2 Open Power Supply Detection (OPSD) The purpose of the Open Power Supply Detection function is to detect if the VDD power circuit is open. It detects if the microcontroller is about to be powered down, to allow software to shutdown the application properly before the Power Down Reset generate by the LVDS. The system is based on a comparison between VREF and VDD. VREF is an analog input which is intended to be directly connected to the power source (see Figure 8). The detection is not dependent on the MCU consumption (not dependent on the voltage drop due to the internal resistor of the power source). To avoid spurious setting of the Power Down Flag due to possible noise (PDF bit in the MISCR register), a margin M is factored into the comparison. The detection is done if: (VREF - VDD) > M The PDF flag can be used to monitor the main supply supervisor function as shown in Figure 9. When (VREF - VDD) > M, the PDF flag is set and an interrupt is generated if the PDIE bit in the MISCR register is set. This feature allows the user program to detect and manage the VDD drop according to the application before the reset generated by the LVDS (See Figure 9). See the Miscellaneous register chapter for more details on the PDF and PDIE bits. 3.1.3 Power Supply Supervisor (PSS) The Power Supply Supervisor function compares the Power Supply to a fixed analog reference voltage (VPSS) (see Figure 10). The output of this comparator is directly connected to the PSSF bit in the MISCR register (read only bit). This feature can be used to monitor the power supply.
The LVDS consists of three main blocks: - Low Voltage Detector (LVD) - Open Power Supply Detection (OPSD) - Power Supply Supervisor (PSS) If the internal oscillator is selected (OSC_SEL pin is tied to VSS), the LVDS, OPSD and PSS functions are always enabled. If an external clock is selected (OSC_SEL tied to VDD), the LVDS, OPSD and PSS are disabled while the external RESET is low and during the first 260 clock cycles (fCPU). They become enabled after this period. Refer to Figure 13. This means an external reset circuit must be provided. However, after this period the LVDS may generate a reset if a power voltage drop occurs. 3.1.1 Low Voltage Detector To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT+ reference value (positive-going input threshold voltage). This means that it secures the power-up as well as the power-down by keeping the ST7 in reset state. The VIT- reference value (negative-going input threshold voltage) for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling The LVD function is illustrated in Figure 7.
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LOW VOLTAGE DETECTOR AND SUPERVISOR (Cont'd) Figure 7. Low Voltage Detector vs Reset
VDD HYSTE RESIS Vhys
VIT+ VIT-
RESET
Figure 8. Open Power Supply Detection: VREF Connections
VREF
SW1
+ Power Down Flag (PDF) generation if (VREF -VDD) >M
RS C VE Power Source VDD
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LOW VOLTAGE DETECTOR AND SUPERVISOR (Cont'd) Figure 9. Open Power Supply Detection (OPSD)
SW1 OPEN (CAPACITOR DISCHARGED)
V' ' VDDRUN HYSTERES IS Vhys VIT+ VIT0V V5 ( ) VE VDDRUN DV = RS .IRUN
SW1 CLOSED
SW1 OPEN
V5 ( )
0V V' ' +VE
V5 ( )
V' '
M 0V RESET Internal RESET PDF RUN RESET Open VDD detection
Figure 10. Power Supply Supervisor system (PSS)
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3.2 RESET SEQUENCE MANAGER The RESET sequence manager includes two reset sources as shown in Figure 11: s External RESET source pulse s Internal LVDS RESET (Low Voltage Detection) These sources act on the RESET PIN and it is always kept low during the delay phase. Figure 11. Reset Block Diagram The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. A 4096 CPU clock cycle delay allows the oscillator to stabilise and to ensure that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles.
VDD
f CPU COUNTER
INTERNAL RESET
RON
RESET
LVD RESET
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RESET MANAGER (Cont'd) ( [ W QDO5 ( 6 ( 7 SL HU Q The RESET pin is both an input and an open-drain output with integrated R ON weak pull-up resistor (see Figure 11). This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. A RESET signal coming from an external source must have a duration of at least tPULSE in order to be recognized. Two RESET sequences can be associated with this RESET source as shown in Figure 12. When the RESET is generated by an internal source, during the two first phases of the RESET sequence, the device RESET pin acts as an output that is pulled low.
Figure 12. External RESET Sequence with internal Clock Selected (OSC_SEL pin tied to VSS)
9' '
VDD nominal VIT+
5 ( 6( 7 5 81
DELAY EXTERNAL RESET SOURCE t PULSE INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
5 81
RESET PIN
Figure 13. External RESET Sequence with External Clock Selected (OSC_SEL pin tied to VDD)
9' '
VDD nominal VIT+
5 ( 6( 7 5 81
INTERNAL RESET 4096 CLOCK CYCLES DELAY 260 CLOCK CYCLES FETCH VECTOR
5 81
EXTERNAL RESET SOURCE
t PULSE
RESET PIN
LVDS, OPSD, PSS
ON
OFF
ON
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RESET MANAGER (Cont'd) ,QW QDO/ RZ 9 RODJ H ' HW L 5 ( 6 ( 7 HU W HFW RQ Two different RESET sequences caused by the internal LVD circuitry can be distinguished: - LVD Power-On RESET - Voltage Drop RESET In the second sequence, a "delay" phase is used to keep the device in RESET state until VDD rises up to VIT+ (see Figure 14). Important: if OSC_SEL pin is HIGH (external clock selected), the LVD Power-On and the Voltage Drop features are disabled during the first 260 clock cycles (fCPU) after reset. This means that an external reset circuitry must be provided to reset the microcontroller.
Figure 14. LVD RESET Sequences when the OSC_SEL pin is tied to GND
VDDnominal VIT+ 9' '
7 ( 6 ( 5 1 2 5 ( : 2 3 ' 9 /
32 : ( 5 2))
5( 6( 7
INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR
581
EXTERNAL RESET SOURCE
RESET PIN
7 KH 2 6 &B6 ( / SL L W W * 1 ' QVL R HG HFW Z L YDW L HU FO QW QDO RFN VHO HG / 9 ' 6 DO D\ V DFW HG 9' ' VDDnominal VIT+ VIT-
5 ( 6( 7 5 81
DELAY
7 ( 6 ( 5 3 2 5 ' ( * $ 7 / 2 9
INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR
581
EXTERNAL RESET SOURCE
RESET PIN
7KH 2 6 &B6 ( / SL L W W 9 6 6 QVL R HG L HU FO QW QDO RFN VHO HG / 9 ' 6 DO D\ V DFW HG HFW Z L YDW
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3.3 MAIN CLOCK CONTROLLER SYSTEM (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows to manage the SLOW power saving mode acting on the SMS bit of the Miscellaneous register (MISCR) and the Main clock-out capability acting on the CKD and CKAFOEN bits of the Smartcard Supply Supervisor Control Register (SSSCR). The main clock of the ST7 can be generated by two different sources (see Figure 17): s an external source s an internal RC oscillator The device is normally operated using an integrated 7.16MHz oscillator, meaning 3.58MHz operating frequency. However, an external clock can be applied, up to 8MHz (4MHz operating frequency). The clock source is selected through the OSC_SEL pin status. ( [ W QDO&O 6 RXU HU RFN FH The OSC_SEL pin status selects the External Clock capability when it is tied to VDD. In this mode, a clock signal with ~50% duty cycle has to drive the OSCIN pin (see Figure 15). ,QW QDO5 & 2 VFLO RU6 RXU HU ODW FH The OSC_SEL pin status selects the Internal RC clock source capability when it is tied to VSS (see Figure 16). Figure 17. Main Clock Controller (MCC) Block Diagram
SMARTCARD interface INTERNA L 7.16 MHz RC OSCILLATOR fOSC DIV 16 LCD and TIMER
Note that OSC_SEL pin contains a pull-down which allows to leave OSC_SEL in high impedance in the application when the internal oscillator is selected. This is mandatory for using the Remote In Situ Programming feature. Figure 15. External Clock
OSCIN
ST7 OSC_SEL
VDD
EXTERNAL SOURCE
Figure 16. Internal RC Oscillator
OSCIN
ST7 OSC_SEL
highZ (internal pulldown is present)
OSCIN
DIV 2
fCPU
OSC_SEL I/O ALTERNATE SC_CK FUNCTION DIV 2 SSSR CK_A CKD FOEN SMS MISCR
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4 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low power mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 4.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 1. 4.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed before entering the edge/ level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 4.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - Writing "0" to the corresponding bit in the status register or - Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) Figure 18. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTE RRUPT PENDING ? Y
FETCH NEXT INSTR UCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTO R
EXECU TE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
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INTERRUPTS (Cont'd) Table 4. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SSS LVDS TIMER EI0 EI1 Reset Software Interrupt Not used Not used External Interrupt Port A7..0 External Interrupt Port B6..0 Not used Not used Not used Not used Timer Underflow Interrupt Not used Not used Not used Smartcard Current Overload Interrupt Power Down Interrupt SSSR MISCR Lowest Priority no no TSCR yes N/A Description Register Label N/A Priority Order Highest Priority Exit from HALT yes no yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FF EFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
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4.4 POWER SAVING MODES 4.4.1 Introduction There are three Power Saving modes. Slow Mode is selected by setting the relevant bits in the Miscellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions. Table 5. Power Saving Modes
Mode Slow fCPU CPU Peripherals switched off. Wake up - External I/O - Timer - LVDS (PDF Flag). - Reset - External I/O - Timer - Reset
Figure 19. Wait Mode Flow Chart
WFI INSTRUCTION
fOSC/32 ON None fOSC/2 OFF None or fOSC/32 - SSS - TIMER 1 OFF - LVDS 2 - LCD
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON OFF CLEARED
Wait
Halt
OFF
N RESET N INTERRUPT Y
Except with external timer clock. If the LVD bit in the MISCR register is reset Note: To reduce power consumption (in Run or Wait modes), the smartcard supply supervisor (SSS) and the LCD can be disabled by software. 4.4.2 Slow Mode In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency except the LCD driver and the 8-bit Timer which have a fixed clock. Slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage. 4.4.3 Wait Mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. The peripherals remain active. During Wait mode, the I bit (CC Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. The MCU will remain in Wait mode until an Interrupt or Reset occurs, the Program Counter then branches to the starting address of the Interrupt or Reset Service Routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 19.
2
1
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON ON SET
IF RESET 4096 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 4.4.4 Halt Mode The Halt mode is the lowest power consumption mode of the MCU. Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering Halt mode, the I bit in the CC Register is cleared so as to enable External Interrupts. If an interrupt occurs, the CPU becomes active. The MCU can exit Halt mode on reception of an interrupt or a reset. Refer to the Interrupt Mapping Table. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. Note: If the LVD bit in the MISCR register is set, the LVDS is not disabled when entering Halt mode.
Figure 20. HALT Flow Chart
HALT INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
OFF OFF OFF CLEARED
N RESET N EXTERNAL INTERRUPT* Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET Y
4096 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
* or some specific interrupts
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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5 ON-CHIP PERIPHERALS
5.1 I/O PORTS 5.1.1 Introduction The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.1.2 Functional Description Each port is associated to 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, for specific port which do not provide this register refer to the I/O Port Implementation section. The generic I/O block diagram is shown on Figure 21. Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Note1: Writing the DR register modifies the latch value but does not affect the pin status. Note2: When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the ports is configured as an output. External interrupt function When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. Each pin can independently generate an Interrupt request. The interrupt sensitivity is given independently according to the description mentioned in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupt section). If more than one input pins are selected simultaneously as interrupt source, these are logically ANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special cares mentioned in the IO port implementation section have to be taken. Output Mode The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pu ll VSS V DD or VSC_PWR Open-drain Vss Floating
Note: In this mode, interrupt function is disabled. Alternate function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. WARNING: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
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I/O PORTS (Cont'd) Smartcard versus Standard I/Os The Smartcard I/O ports differ from the standard I/ O ports in that they have a different power supply: the output buffers and the input Schmitt trigger are supplied by VSC_PWR for the Smartcard I/Os and by VDD for the Standard I/Os. For Smartcard I/Os, the Schmitt trigger is designed to guarantee output levels compatible with VDD for VSC_PWR =5V or 3V. Figure 21. I/O Block Diagram
ALTERNATE OUTPUT ALTERNATE ENABLE DR 1 V DD or VSC_PWR P-BUFFER (OPTION*) PULL-UP (OPTION*)
Caution: When the SSS regulator is deactivated (bit SSSEN=0), the Smartcard I/O ports cannot be used correctly (VSC_PWR=VSS). In this case, special care is required when manipulating external interrupts: As Smartcard I/Os are always tied to ground, they may mask interrupts on other I/O lines of the same port.
0
VDD or VSC_PWR
DDR PULL-UP CONDITION If implemented OR SEL N-BUFFER DDR SEL VDD or VSC_PWR PULL-DOWN CONDITION DR SEL 1 0 ANALOG INPUT DIODES (OPTION*) PAD
OR
INTERRUPT
Table 6. Port Mode Options
Configuration Mode Floating Input Pull-up with Interrupt Push-pull Open Drain (logic level) Output Push-pull with pull-up Open Drain (logic level) with pull-up True Open Drain NI - not implemented Off - implemented not activated Pull-Up Off On Off P-Buffer Off On Diodes
DATA BUS
ALTERNATE INPUT * SEE TABLE BELOW
On Off On On Off NI On - implemented and activated
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I/O PORTS (Cont'd) 5.1.3 I/O Port Implementation The I/O port register configurations are summarised as follows. Standard Ports PA0:7, PB5 (supplied by VDD)
MODE floating input pull-up input with interrupt open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
PB1 (Smartcard Data supplied by VSC_PWR)
MODE pull-up input pull-up input with interrupt open drain output with pull-up push-pull output with pull-up DDR 0 0 1 1 OR 0 1 0 1
PB6 (supplied by VDD)
MODE floating input pull-down input with interrupt open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 22 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 22. Interrupt I/O Port State Transition
01
INPUT pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
PB0, 2, 3, 4 (supplied by VSC_PWR)
MODE floating input pull-up input with interrupt open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
XX
= DDR, OR
Table 7. Port Configuration
Input Port Port A Pin name OR = 0 PA7:0 PB6 PB5 PB4:2 (SC*) PB1 (SC*) PB0 (SC*) floating floating floating floating pull-up floating OR = 1 pull-up interrupt pull-down interrupt pull-up interrupt pull-up interrupt pull-up interrupt pull-up interrupt OR = 0 open drain open drain open drain open drain pull-up open drain open drain OR = 1 push-pull push-pull push-pull push-pull pull-up push-pull push-pull Output
Port B
* Note: Smartcard I/Os supplied by VSC_PWR.
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I/O PORTS (Cont'd) 5.1.4 Register Description ' $ 7 $ 5 ( * ,6 7 ( 5 ' 5 Port x Data Register PxDR with x = A or B. Note: In Port B, PB[7] is unused. Read/Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 7 D0 O7 O6 O5 O4 O3 O2 O1 O0 0
0: Input mode 1: Output mode 2 3 7 ,2 1 5 ( * ,6 7( 5 2 5 Port x Option Register PxOR with x = A or B. Read/Write Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A or B. Read/Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bit 7:0 = OR[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up (or pull-down for PB6) with interrupt capability or the floating (pull-up for PB1) configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software.
Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software.
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I/O PORTS (Cont'd) Table 8. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0
Reset Value of all IO port registers 0000h 0001h 0002h 0004h 0005h 0006h PADR PADDR PAOR PBDR PBDDR PBOR
0
0
0
0
0
0
0
0
MSB
LSB
-
MSB
LSB
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5.2 MISCELLANEOUS REGISTER The miscellaneous register allows control over several features such as the external interrupts or the I/O alternate functions. 5.2.1 I/O Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the IPB and IS[1:0] bits of the Miscellaneous register (Figure 23). Up to 2 fully independent external interrupt source sensitivities are allowed. Each external interrupt source can be triggered by four different events on the pin: s Falling edge s Rising edge s Falling and rising edge Figure 23. External Interrupt Sources vs MISCR
EI1 INTERRUPT SOURCE PB6 SOURCES PB0 IPB EI0 INTERRUPT SOURCE PA7 SOURCES PA0
Falling edge and low level To guarantee the functionality, a modification of the sensitivity in the MISC register can be done only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on programming. Caution: Take care when changing the value of the IPB bit as, in some cases, an interrupt will be generated by the edge resulting from the change.
s
5.2.2 Slow mode and VDD Supply Monitoring The MISCR register manages SLOW mode selection and the LVDS VDD monitoring interrupt. Refer to the register description.
MISCR IS1 IS0
SENSITIVIT Y CONTROL
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MISCELLANEOUS REGISTER (Cont'd) 0 ,6 &( / / $ 1 ( 2 8 6 5 ( * ,6 7 ( 5 0 ,6 &5 Read/Write Reset Value: x000 0000 (x0h) (for bit 7, the reset value depends on VDD)
7 6 5 IPB 4 IS1 3 IS0 2 PDIE 1 PDF 0 SMS External Interrupt Sensitivity IS1 IS0 MISCR.IPB=0 0 0 1 PSSF LVD 1 IS1 0 0 1 1 0 1 0 1 IS0 0 1 0 1 Falling edge & low level Rising edge only Falling edge only MISCR.IPB=1 Rising edge & high level Falling edge only Rising edge only
Rising and falling edge External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bit 7 = PSSF Power Supply Supervisor Flag This bit is set and cleared by hardware. 0: VDD is greater than VPSS. 1: VDD is less than VPSS. Bit 6= LVD LVD ON during HALT mode This bit is set and cleared by software. This bit is used to keep the LVD active during HALT mode. 0: LVD switched off in HALT mode (reset state). 1: LVD active in HALT mode. Bit 5 = IPB Interrupt polarity for port B This bit is used to reverse the external interrupt sensitivity polarity of the port B[6:0] pins. It is set and cleared by software. 0: Standard sensitivity polarity 1: Reversed sensitivity polarity Note: See IS[1:0] bit description for more details. This bit can be written only when the I bit of the CC register is set to 1 (if interrupts are masked). Bit 4:3 = IS[1:0] EI0 and EI1 sensitivity These bits are used to program the interrupt sensitivity of the following external interrupts: - EI1 (port B[6:0]) - EI0 (port A[7:0]) These 2 bits can be written only when the I bit of the CC register is set to 1 (interrupt masked).
Bit 2 = PDIE Power Down Interrupt Enable This bit is set and cleared by software. 0: Power down interrupt disabled 1: Power down interrupt enabled Bit 1 = PDF Power Down Flag This bit is set and cleared by software or set by hardware if (VREF - VDD) > M. If the PDIE bit is set, an interrupt is generated when PDF is set (sensitivity is high level). It can be cleared only by software writing zero. It can also be set by software, generating an interrupt if PDIE is enabled. 0: (VREF - VDD) < M : No open VDD circuit detected 1: (VREF - VDD) > M : Open VDD circuit detected. Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU = fOSC / 32 See low power mode and MCC chapters for more details.
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5.3 8-BIT TIMER (TIM8) 5.3.1 Introduction The 8-Bit Timer on-chip peripheral (TIM8) is a free running downcounter based on an 8-bit downcounter with a 9-bit programmable prescaler. 5.3.2 Main Features s Timeout downcounting mode with up to 16-bit accuracy s External counter clock source (valid also in HALT mode) s Interrupt capability on counter underflow s Output signal generation s External pulse length measurement s Time base interrupt The timer can be used in WAIT and HALT modes and to wake up the MCU.
Figure 24. Timer Block Diagram
fOSC TIMIO 7 DIV2 fCPU DIV16 fEXT 7 OEN TOUT DOUT UDF ETI PSE PS1 ALTERNATE FUNCTION
LATCH
8-BIT COUNTER
0 fCOUNTER
TCR
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
UNDERFLOW 0 PS0 TSCR
UDF INTERR UPT
fTIMER
RELOAD
PSCR 8 5 2 0
PSCR8 PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0 fTIMER fTIMER/8 fTIMER/64 fTIMER/512 PROGRAMMABLE PRESCALER
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8-BIT TIMER (Cont'd) 5.3.3 Counter/Prescaler Description Counter The free running 8-bit downcounter is fed by the output of the programmable prescaler, and is decremented on every rising edge of the f COUNTER clock signal. It is possible to read or write the contents of the counter on the fly, by reading or writing the timer counter register (TCR). When a counter underflow occurs, the counter is automatically reloaded with the value FFh. Counter clock and prescaler The counter clock frequency is given by: fCOUNTER = fTIMER / 8PS[1:0] where fTIMER can be: - fCPU/16 - fEXT (input on TIMIO pin) - fCPU/16 gated by TIMIO pin
Table 13 lists the values that fCOUNTER can take if fTIMER is fCPU/16. Table 9. fcounter values for a fcpu=3.58MHz
fcounter 224 kHz 28 kHz 3.5 kHz 437 Hz PS0 0 1 0 1 PS1 0 0 1 1
The timer input clock (fTIMER ) feeds the 9-bit programmable prescaler. The prescaler output can be programmed by selecting one of the 4 available prescaler taps using the PS[1:0] bits in the Status/ Control Register (TSCR). Thus the division factor of the prescaler can be set to 8n (where n equals 0, 1, 2 or 3). See Figure 38. The clock input is enabled by the PSE (Prescaler Enable) bit in the TSCR register. When PSE is reset, the counter is frozen and the prescaler is loaded with the value 1FFh. When PSE is set, the prescaler and the counter run at the rate of the selected clock source. Counter and Prescaler Initialization After RESET, the counter and the prescaler are initialized to FFh and 1FFh respectively. The 9-bit prescaler can be initialized separately to 1FFh by clearing the PSE bit. Direct write access to the prescaler is not possible. The 8-bit counter can be initialized separately by writing to the TCR register.
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8-BIT TIMER (Cont'd) 5.3.4 Functional description 5.3.4.1 8-bit counting and interrupt capability on counter underflow Whatever the division factor defined for the prescaler, the Timer Counter works as an 8-bit downcounter. The input clock frequency is user selectable using the PS0 and PS1 bits. When the downcounter underflows (transition from 00h to FFh), the UDF (Timer Underflow) bit in the TSCR is set. If the ETI (Enable Timer Interrupt) bit in the TSCR is also set, an interrupt request is generated. The Timer interrupt can be used to exit the MCU from WAIT or HALT mode. The TCR can be written at any time by software to define a time period ending with a UDF event, and therefore manage delay or timer functions. UDF is set when the counter underflows (clock pulse creating the transition from 00h to FFh); however, it may also be set by setting bit 4 of the TSCR register. The UDF bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded with 0FFh, while the 9-bit prescaler is loaded with 1FFh, and the TSCR register is loaded with 050h. This means that the Timer is stopped (PSE="0") and the timer interrupt is disabled. Note: A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the UDF bit is not set until the 8-bit counter underflows again. Application Notes - A time base interrupt can be created by using the UDF interrupt to generate interrupts at regular time intervals. With the maximum prescaler ratio set, the maximum period between two UDF flags is: 512/fTIMER If we consider the previous example: (fTIMER=fCPU/16) we have (512*16) / fCPU (2.3 ms for a fCPU of 3.58MHz). With the minimum prescaler ratio set, the minimum step of the 8-bit downcounter, i.e the res-
olution, is 1/fTIMER, that means 16 / fCPU (4.5 s for a fCPU=3.58MHz). - When the maximum division factor (512) is set, the input clock to the 8-bit downcounter is the 9th and last bit of the prescaler. This means, the 9bit prescaler and the 8-bit counter are serialized and can be considered as a 16-bit counter with a frequency of fTIMER/512. 5.3.4.2 Gated mode (TOUT = "0", DOUT = "1") Figure 25. fTIMER Clock in Gated Mode
fCPU/16 fTIMER TIMIO fEXT
In this mode, the prescaler is decremented by the Timer clock input, but only when the signal on the TIMIO pin is held high (fCPU/16 gated by TIMIO). See Figure 39 and Figure 40. This mode is selected by clearing the TOUT bit in the TSCR register (i.e. as input) and setting the DOUT bit. Figure 26. .Gated Mode Operation
Counter Value xx1 Value 1
xx2
Value 2
TIMIO Pin Pulse Length 1
Timer Clock
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8-BIT TIMER (Cont'd) 5.3.4.3 Event counter mode (TOUT = "0", DOUT = "0") Figure 27. fTIMER Clock in Event Counter Mode
TIMIO
fTIMER
In this mode, the TIMIO pin is the input clock of the Timer prescaler which is decremented on every rising edge of the input clock (allowing event count). See Figure 41 and Figure 42. This mode is selected by clearing the TOUT bit in the TSCR register (i.e. as input) and clearing the DOUT bit. Figure 28. Event Counter Mode Operation
Counter Value xx1 Value 1
In Output mode, the TIMIO pin is connected to the DOUT latch, hence the Timer prescaler is clocked by the prescaler clock input (fCPU /16). See Figure 43. The user can select the desired prescaler division ratio through the PS1 and PS0 bits of the TSCR register. When the TCR count underflows, it sets the UDF bit in the TSCR. The UDF bit can be tested under program control to perform a timer function whenever it goes high and has to be cleared by the user. The low-to-high UDF bit transition is used to latch the DOUT bit of the TSCR and, if the OEN bit is set, DOUT is transferred to the TIMIO pin. This operating mode allows external signal generation on the TIMIO pin. See Figure 44. This mode is selected by setting the TOUT bit in the TSCR register (i.e. as output) and setting the DOUT bit to output a high level or clearing the DOUT bit to output a low level Figure 30. Output Mode Operation
Counter FFh
xx2 TIMIO Pin
Value 2 At each underflow DOUT has to be copied to the TIMIO pin
TIMIO Pin 1
5.3.4.4 Output mode (TOUT = "1", DOUT = "data out") Figure 29. Output Mode Control
1 st downcount : Default output value is 0
TIMIO
ALTERNATE FUNCTION
TOUT DOUT 0 0 0 1 0 1
Timer Function Event Counter (input) Gated input (input) Output "0" (output) Output "1" (output)
Application External counter clock source External Pulse length measurement Output signal generation
LATCH
OEN
DOUT
UDF
1 1
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8-BIT TIMER (Cont'd) 5.3.5 Register Description PRESCALER COUNTER REGISTER (PSCR) Read only Reset Value: 1111 1111 (FFh)
7 0
Bit 5 = DOUT Data Output. Data sent to the timer output when UDF is set high (output mode only). Input mode selection (input mode only). Bit 4 = UDF: Timer Underflow. A low-to-high transition indicates that the timer count register has underflowed. It means that the TCR value has changed from 00h to FFh. This bit must be cleared by user software. 0: Counter has not underflowed 1: Counter underflow occurred (reset state) Bit 3 = ETI: Enable Timer Interrupt. When set, enables the timer interrupt request. If ETI=0 the timer interrupt is disabled. If ETI=1 and UDF=1 an interrupt request is generated. 0: Interrupt disabled (reset state) 1: Interrupt enabled Bit 2 = PSE: Prescaler Enable. Used to initialize the prescaler and inhibit its counting. When PSE="0" the prescaler is set to 1FFh and the counter is inhibited. When PSE="1" the prescaler is enabled to count downwards. As long as PSE="0" both counter and prescaler are not running 0: Counting disabled (reset state) 1: Counting enabled Bit 1:0 = PS1:0 Prescaler Mux. Select. These bits select the division ratio of the prescaler register.
fTIMER divided by 1 8 64 512 PS1 0 0 1 1 PS0 0 1 0 1
PSCR8 PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1
Bit 7:0 = PSCR[8:1] Prescaler MSB. TIMER COUNTER REGISTER (TCR) Read / Write Reset Value: 1111 1111 (FFh)
7 TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 0 TCR0
Bit 7:0 = TCR[7:0] Timer counter bits. TIMER STATUS CONTROL REGISTER (TSCR) Read/Write Reset Value: 0101 0000 (50h)
7 OEN TOUT DOUT UDF ETI PSE PS1 0 PS0
Bit 7 = OEN Output Enable. In output mode, this bit allows DOUT to be send to the timer output. It has no effects in INPUT mode. 0: Output disabled (reset state) 1: Output enabled Bit 6 = TOUT Timer Output Control. When low, this bit selects the input mode for the TIMER pin. When high the output mode is selected. 0: Input mode 1: Output mode (reset state)
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8-BIT TIMER (Cont'd) Table 10. 8-Bit Timer Register Map and Reset Values
Address (Hex.) 0031h 0032h 0033h Register Label PSCR Reset Value TCR Reset Value TSCR Reset Value 7 PSCR8 1 TCR7 1 OEN 0 6 PSCR7 1 TCR6 1 TOUT 1 5 PSCR6 1 TCR5 1 DOUT 0 4 PSCR5 1 TCR4 1 UDF 1 3 PSCR4 1 TCR3 1 ETI 0 2 PSCR3 1 TCR2 1 PSE 0 1 PSCR2 1 TCR1 1 PS1 0 0 PSCR1 1 TCR0 1 PS0 0
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5.4 32 x 4 LCD DRIVER 5.4.1 Introduction The LCD driver controls up to 32 segments and 4 backplanes for driving up to 32x4 (128) LCD segments. The LCD input clock can be divided by a selected ratio depending on the required frame frequency. Figure 31. LCD Driver Block Diagram The parameters to display are stored in a 16-bytes LCD dual port RAM. The peripheral can be switched off by software to reduce power consumption when not in use. No external capacitor/resistor network is required as it is integrated on the chip.
fLCD RING COUNTER f osc/2 FREQUENCY SELECTION fLCD 4 COM[3:0] COM DRIVERS
COM3 COM2 COM1 COM0
SEG31 fLCD SEG[31:0] SEG DRIVERS ...
SEG0
32 COM[3:0]
To COM and SEG Drivers
VDD 2VDD/3 VDD/3 Vss
VDD
MUX 128 to 32 REFERENCE VOLTAGE GENERATOR LCD RAM 32x4 bits VSS
Address Bus Data Bus
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LCD DRIVER (Cont'd) 5.4.2 Segment and Common signals Each picture element of the LCD panel is turned on when the differential voltage between the segment signal and the common signal rises above a certain threshold voltage. It is turned off when the voltage is below the threshold voltage. Common signals determine the select timing within a frame cycle. The common signals have identical waveforms, but different phases. Each common signal has the highest amplitude only in the corresponding phase of a frame cycle. At the other phases, the signal amplitude is lower (2/3 - 1/3). A picture element can only be turned on with high signal amplitude. The LCD driver has 32x4 bits of display memory. The corresponding address locations are read out automatically in synchronisation with the select timing of COM0, COM1, COM2 and COM3. Figure 32. Waveforms of LCD Outputs
LCD clock COMi
for a short period of time when the levels of common and segment lines change. This method combines low source impedance for fast switching of the LCD with high source impedance for low power consumption. When the LCD is disabled (bit LCDEN=0), the internal resitive network is also switched off for minimum power consumption. Figure 33. LCD Reference Voltage generation
RL ON
LCDE
VDD
RL RL
RH RH
C
VDD
C
2VDD/3
RL
RH
C
VDD/3
VSS
VDD 2/3 1/3
VSS
GND SEGi
COM ON COM OFF
VDD 2/3 1/3 GND
SEG ON SEG OFF
5.4.3 Reference Voltages The display voltage levels are supplied by an internal resistor divider network as shown in Figure 47 This LCD driver generates 4 reference voltages from VSS and VDD through an internal RC divider network. In order to increase current during transitions and to reduce consumption in static state, two resistive networks are used. The high resistive divider is permanently switched on during the LCD operation. The low resistive divider is only switched on
5.4.4 Display Example The example in Figure 48 shows a sequence of two identical frames containing the waveforms displaying a "4" in a seven-segment display. In each TFRAME period, the LCD driver automatically switches on each of the four COM signals for one TLCD period. COM0 is on in the first period, COM1 in the second period and so on. To switch them on, the waveform goes above and below the threshold voltages. When the waveform is within the thresholds, the COM is off. The SEG signals are controlled by software by programming the display memory. - SEG 0 is off during the first period and on for the remaining three periods. - SEG 1 is off during TLCD periods 1, 2, and 4 and on for T LCD period 3. To program the display memory for this example, software must write 00h in locations 0140h -0143h and 01h in locations 144h through 0147h (refer to Section 5.4.7)
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LCD DRIVER (Cont'd) Figure 34. Mux Waveforms Example
Frame 1
TFRAME = 4TLCD
Frame 2
fLCD
VDD 2/3 1/3 GND VDD 2/3 1/3 GND
COM0
COM1
COM3 COM2 COM3 SEG1 SEG0
SEG1
COM2 SEG0 SEG1 COM1
COM2
COM1
VDD 2/3 1/3 GND VDD 2/3 1/3 GND
SEG0
SEG0
COM3
COM0
SEG0
VDD 2/3 1/3 GND VDD 2/3 1/3 GND VDD 2/3 1/3 GND -1/3 -2/3 -VDD
SEG1
COM 0-SEG0
COM ON COM OFF COM OFF COM OFF COM ON COM OFF COM OFF COM OFF SEG OFF SEG ON SEG ON SEG ON SEG OFF SEG ON SEG ON SEG ON
VDD 2/3 COM 1-SEG0 1/3 GND -1/3 -2/3 -VDD COM OFF COM ON SEG OFF SEG ON COM OFF COM OFF COM OFF COM ON COM OFF COM OFF SEG ON SEG ON SEG OFF SEG ON SEG ON SEG ON
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LCD DRIVER (Cont'd) 5.4.5 Clock generation Figure 35. LCD Clock Generation Diagram LCDCR
FS2 FS1 FS0 LCDE
fOSC/2 2MHz FS2 1 1 1 0 FS1 1 0 0 1 FS0 0 1 0 1 Ratio 8192 4096 2048 1024 fLCD 244Hz 488Hz 977Hz 1.953kHz fframe 61Hz 122Hz 244Hz 488Hz
FS2 FS1 FS0
fOSC /2
RATIO DIVIDER
f LCD
fOSC/2 1MHz FS2 1 1 0 0 FS1 0 0 1 1 FS0 1 0 1 0 Ratio 4096 2048 1024 512 fLCD 244Hz 488Hz 977Hz 1.953kHz fframe 61Hz 122Hz 244Hz 488Hz
The frequency divider (FS[2:0]) should be chosen according to the input frequency and the required frame frequency, A compromise should be found between a sufficient frame frequency display on the LCD for correct visualisation and a low frame frequency for low consumption. Below are the approximate LCD and frame frequencies resulting from the input frequencies selected using the FS[2:0] bits. Note: The LCD frequency (f LCD) must not exceed 2kHz.
fOSC/2 3.58MHz FS2 1 1 1 1 FS1 1 1 0 0 fOSC/2 4MHz FS2 1 1 1 1 FS1 1 1 0 0 FS0 1 0 1 0 Ratio 16384 8192 4096 2048 fLCD 244Hz 488Hz 977Hz 1.953kHz fframe 61Hz 122Hz 244Hz 488Hz FS0 1 0 1 0 Ratio 16384 8192 4096 2048 fLCD 213.5Hz 427Hz 874Hz 1.748kHz fframe 53Hz 109Hz 218.5Hz 437Hz
fOSC/2 500kHz FS2 1 0 0 0 FS1 0 1 1 0 fOSC/2 225kHz FS2 0 0 0 0 FS1 1 1 0 0 FS0 1 0 1 0 Ratio 1024 512 256 128 fLCD 244Hz 488Hz 977Hz 1.953kHz fframe 61Hz 122Hz 244Hz 488Hz FS0 0 1 0 1 Ratio 2048 1024 512 256 fLCD 244Hz 488Hz 977Hz 1.953kHz fframe 61Hz 122Hz 244Hz 488Hz
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LCD DRIVER (Cont'd) 5.4.6 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000 0000 (00h)
7 6 5 4 3 FS2 2 FS1 1 FS0 0 LCDE
5.4.7 LCD RAM Description The 16-byte LCD RAM is located in memory from address 0140h to address 014Fh. Each bit of the LCD RAM is mapped to one picture element of the LCD panel. If a bit is set, the corresponding picture element is switched on, otherwise it is switched off. After reset, the LCD RAM is not initialized and its content is indeterminate.
Addr. 7 S7 S15 S23 S31 S7 S15 S23 S31 S7 S15 6 S6 S14 S22 S30 S6 S14 S22 S30 S6 S14 S22 S30 S6 S14 S22 S30 5 S5 S13 S21 S29 S5 S13 S21 S29 S5 S13 S21 S29 S5 S13 S21 S29 4 S4 S12 S20 S28 S4 S12 S20 S28 S4 S12 S20 S28 S4 S12 S20 S28 3 S3 S11 S19 S27 S3 S11 S19 S27 S3 S11 S19 S27 S3 S11 S19 S27 2 S2 S10 S18 S26 S2 S10 S18 S26 S2 S10 S18 S26 S2 S10 S18 S26 1 S1 S9 S17 S25 S1 S9 S17 S25 S1 S9 S17 S25 S1 S9 S17 S25 0 S0 S8 S16 S24 S0 S8 S16 S24 S0 S8 S16 S24 S0 S8 S16 S24 0140h
COM0 COM1 COM2 COM3
Bit 7:4 = Reserved, Must always be cleared Bit 3:1 = FS2:0 Frame Frequency selection These bits allow to select the LCD frame frequency. It controls the ratio between the input clock (fOSC/2) and the LCD output clock (fLCD). These bits are set and cleared by software.
Ration Divider 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0
0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h
014Ah S23 014Bh S31 014Ch S7 014Dh S15 014Eh S23 014Fh S31
Bit 0 = LCDE LCD enable This bit is set and cleared by software. 0: LCD disabled 1: LCD enabled While the LCD is disabled (LCDE bit cleared), all Segment and Common pins are high impedance.
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LCD DRIVER (Cont'd) Table 11. LCD Driver Register Map and Reset Values
Address (Hex.) 0024h 0140h to 014Fh
Register Label LCDCR Reset Value LCDRAM Reset Value
7
6
5
4
3 FS2 0 Seg X COMi X
2 FS1 0 Seg X COMi X
1 FS0 0 Seg X COMi X
0 LCDE 0 Seg X COMi X
0 Seg X COMi X
0 Seg X COMi X
0 Seg X COMi X
0 Seg X COMi X
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5.5 SMARTCARD SUPPLY SUPERVISOR (SSS) 5.5.1 Introduction The Smartcard Supply Supervisor (SSS) allows the VSC_PWR Smartcard supply to be switched on and off by software and protects the smartcard from overload. In addition, the SSS supplies power to the I/O lines used to interface the smartcard. This means that no external components are needed for adapting the interface to the levels required for interfacing the smartcard, except a capacitor on the SC_PWR output. 5.5.2 Main Features s Software power-on/off control s Hardware cut-off in case of output current overload s Grounded output level when turned-off s Low consumption mode 5.5.3 General description The SSS generates the Smartcard SC_PWR supply from the MCU VDD supply. When disabled, the regulator ties the output SC_PWR line to ground, and is placed in low power mode. At the same time, the interface I/O lines are also tied to ground. In case of current overload on the output SC_PWR, the output level drops due to internal impedance of the regulator. The associated Current Overload detector switches-off the SC_PWR supply and sets a flag into the Status/Control Register. Figure 50 shows the Smartcard Supply Supervisor (SSS) block diagram.
Figure 36. Smartcard Supply Supervisor (SSS) Block Diagram
VOLTAGE REGULATOR
3V 0
VDD +
MCU VDD
Reference voltage
5V
1
SC_PWR
CURRENT OVERLOAD DETECTOR + -
V DD Control Logic
Reference Voltage
SC I/Os
SSSCR
I/O
0 CKODCK_AF OVLD OEN F
fOSC /2 fOSC/4
OVLD OVLD SSSR SSS IE EN EN OVLD INTERRUP T
Control Logic SC_CK
0 1
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SMARTCARD SUPPLY SUPERVISOR (Cont'd) 5.5.4 Functional Description The core of the SSS is the internal reference voltage generator that is used for the output voltage level regulation and for the Current Overload detection. Output regulation is achieved from the MCU VDD with a follower transistor used as output stage, associated to a feedback regulation. Software control through the Status/Control register allows software to: s Turn-on / turn-off the SSS s Enable the overload detector s Enable interrupt in case of overload Smartcard Power Supply When disabled, the whole SSS is stopped in order to achieve minimum consumption. The SC_PWR line is tied to ground, and the I/O lines supplied by SC_PWR, are also tied to ground. When the SSS module is enabled, the SC_PWR line provides a regulated voltage to the smartcard, and the I/O lines have a logic "1" level identical to the smartcard supply ensuring a safe interface. Current Overload protection When a current overload occurs on the SC_PWR supply output, SC_PWR level drop is detected by the Current Overload detector when enabled. As a consequence, the SSS is turned-off with the SC_PWR line tied to ground and the SSSEN bit is cleared. On top of that, the OVLD flag is set into the Status/Control Register and an interrupt request can be initiated. Note: The Current Overload detector must be enabled by setting OVLDEN bit only after setting the SSSEN bit.
Figure 37. Current Overload Detection
SHORT CIRCUIT ISC_PWR
0 mA VSC_PWR
VOVLD
0V
OVLDF FLAG
Switching SC_PWR from 3V to 5V output and vice versa The usual (and safe) procedure is to test the card at 3V before selecting 5V output. The application should avoid making a direct transition from 5V to 3V as a delay is required before the 3V level is reached (the delay depends on the external capacitor and card type). For a controlled transition from 5V to 3V it is recommended to clear the SSSEN bit to tie the SC_PWR to ground before enabling 3V output. See Figure 52.
Figure 38. Recommended transitions when switching the voltage regulator (SSSR bit).
VSC_PWR 5V
3V
0V SSSR =0 SSSEN=1 SSSR=1 SSSEN=1 SSSR=1 SSSEN=0 SSSR=0 SSSEN=1
t
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SMARTCARD SUPPLY SUPERVISOR (Cont'd) 5.5.5 Register Description CONTROL/STATUS REGISTER (SSSCR) Read/Write Reset Value: 0000 0000 (00h)
7 0 6 CKOD 5 CK_A FOEN 4 OVLDF 3 OVLDIE 2 OVLDEN 1 SSSR 0 SSSEN
when SC_PWR is under the Overload Voltage Level. This bit can only be cleared by software. 0: No Current Overload 1: Current Overload Bit 3 = OVLDIE Overload interrupt enable This bit is set and cleared by software. 0: OVLD interrupt disabled. 1: OVLD interrupt enabled. Bit 2= OVLDEN Current overload detector enable This bit is set and cleared by software. This bit must be set only when SSSEN =1. 0: Current Overload Detection disabled. 1: Current Overload Detection enabled. Bit 1 = SSSR Smartcard supply regulation This bit is set and cleared by software. Refer to Figure 52 for recommended transitions. 0: The regulation voltage output is 3V. 1: The regulation voltage output is 5V. Bit 0 = SSSEN SSS module enable This bit can only be set by software. It can be cleared by software. It is cleared by hardware when OVLDF=1 (current overload condition). 0: SSS is disabled. 1: SSS is enabled.
Bit 7 = Reserved, forced by hardware to 0. Bit 6 = CKOD Clock output division This bit is set and cleared by software. It selects the frequency division factor of the SC_CK output clock. 0: SC_CK clock output frequency = fosc /2. 1: SC_CK clock output frequency = fosc /4. Bit 5 = CK_AFOEN Clock AF output enable This bit is set and cleared by software. 0: The SC_CK alternate function is disabled. The I/O port is free for general purpose I/O. 1: The SC_CK alternate function is enabled. The clock is output on the I/O port. Bit 4 = OVLDF Overload flag This bit is set by hardware when the SC_PWR output voltage drops due to current overload. It is set when a falling edge is detected on SC_PWR and
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SMARTCARD SUPPLY SUPERVISOR (Cont'd) Table 12. SSSCR Register Map and Reset Values
Address (Hex.) 0025h Register Name SSSCR Reset Value 7 6
CKD 0
5
CK_AFOEN 0
4
OVLDF 0
3
OVLDIE 0
2
OVLDEN 0
1
SSSR 0
0
SSSEN 0
0
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6 INSTRUCTION SET
6.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do Table 13. ST7 Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination/ Source
Pointer Address (Hex.)
Pointer Size (Hex.) +0 +1
Length (Bytes)
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC-128/PC+127 1) PC-128/PC+127 1) 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word
+1 +2 + 0 (with X register) + 1 (with Y register) +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
btjt [$10],#7,skip 00..FF
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (Cont'd) 6.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
6.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 6.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 6.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
6.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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ST7 ADDRESSING MODES (Cont'd) 6.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 14. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Addition/subtraction operations Bit Compare Function
6.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Available Relative Direct/ Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear
Functio n Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine
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6.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Code Condition Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION GROUPS (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) H= 1? H= 0? I=1? I=0? N= 1? N= 0? Z=1? Z=0? C= 1? C= 0? Unsigned < Jmp if unsigned >= Unsigned > jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+ C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C
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INSTRUCTION GROUPS (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C <= Dst <= C C => Dst => C S = Max allowed A=A-M-C C=1 I=1 C <= Dst <= 0 C <= Dst <= 0 0 => Dst => C Dst7 => Dst => C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src H I N Z C
Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt
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7 ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATINGS This product contains devices for protecting the inputs against damage due to high static voltages, however it is advisable to take normal precautions to avoid appying any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that VI and VO be higher than VSS and lower than V DD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD or VSS).
Symbol VDD - VSS VIN VOUT ESD IVDD_i IVSS_i Supply voltage Input voltage Output voltage ESD susceptibility Total current into VDD_i (source) Total current out of VSS_i (sink) Ratings
Power Considerations. The average chip-junction temperature, TJ, in Celsius can be obtained from: TJ = TA + PD x RthJA Where: TA = Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). PD = PINT + PPORT. PINT = IDD x VDD (chip internal power). PPORT =Port power dissipation determined by the user)
Value 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 3500 150 150 Unit V V V V mA
Note: Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
General Warning: Direct connection to VDD or V SS of the RESET and I/O pins could damage the device in case of program counter corruption (due to unwanted change of the I/O configuration). To guarantee safe conditions, this connection has to be done through a typical 10K pull-up or pull-down resistor.
Thermal Characteristics
Symbol RthJA T Jmax TSTG PD Ratings Package thermal resistance Max. junction temperature Storage temperature range Power dissipation TQFP64 EQFP64 Value 60 N/A 150 -65 to +150 500 Unit C/W C C mW
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7.2 RECOMMENDED OPERATING CONDITIONS
GENERAL Symbol VDD f RCINT fOSC TA Parameter Supply voltage Internal oscillator frequency External clock source Ambient temperature range >0 0 Conditi ons see Figure 39 Min 4.0 7.16 25% 8 70 Typ Max 6.6 Unit V MHz C
Figure 39. Maximum Operating Frequency (fOSC ) Versus Supply Voltage (VDD) (Operating conditions TA = 0 to +70C unless otherwise specified)
I2 6 &
> +] @ 0
FUNCTIONALI TY NOT GUARAN TEED IN THIS AREA
FUNCTI ONALITY GUARANTEE D IN THIS AREA FOR 3V AND 5V CARDS
fRCINT
Main Supply Voltage [VDD]
FUNCTIONA LITY GUARANTE ED IN THIS AREA WITH FOR 3V CARDS ONLY (ISO/IE C7816-3 CLASS B)
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RECOMMENDED OPERATING CONDITIONS (Cont'd) (Operating conditions TA = 0 to +70C unless otherwise specified)
CURRENT INJECTION ON I/O PORT AND CONTROL PINS Symbol Parameter Conditi ons VEXTERNAL > VDD (Standard I/Os) VEXTERNAL > VSC_PWR (Smart card I/Os) VEXTERNAL < VSS IINJTotal negative injected current (2) Digital pins Analog pins 1.6 0.8 mA Min Typ Max Unit
IINJ+
Total positive injected current
(1)
5*
mA
Note 1: Positive injection The IINJ+ is done through protection diodes insulated from the substrate of the die. Note 2: For SC I/Os, VSC_PWR has to be considered. Note 3: Negative injection - The IINJ- is done through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small leakage (few A) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital structure, but it acts on the analog line according to the impedance versus a leakage current of few A (if the MCU has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals applied to the component must have a maximum impedance close to 50K. Location of the negative current injection: - Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog input pins. General Note: When several inputs are submitted to a current injection, the maximum I INJ is the sum of the positive (resp. negative) currrents (instantaneous values).
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RECOMMENDED OPERATING CONDITIONS (Cont'd) (TA=0 to +70oC, VDD-VSS=6V unless otherwise specified)
Symbol Parameter Supply current in RUN mode
1) 1)
Conditio ns
Min
Typ. 3 0.4 0.6 0.3 300 0
Max 6
Unit mA mA mA mA A A
IDD
Supply current in SLOW mode Supply current in WAIT mode 2)
fOSC = 8 MHz
Supply current in SLOW WAIT mode 3) Supply current in HALT mode, LVD enILOAD = 0mA abled. 4) Supply current in HALT mode LVD disabled. 4)
Notes: 1. CPU running with memory access, all I/O pins in input mode with a static value at V DD or VSS; clock input (OSC1) driven by external square wave, LVD enabled. 2. All I/O pins in input mode with a static value at VDD or VSS; clock input (OSC1) driven by external square wave, LVD enabled. 3. WAIT Mode with SLOW Mode selected, LVD enabled. Based on characterisation results, not tested. 4. All I/O pins in input mode with a static value at VDD or VSS, I/O PORT CHARACTERISTI CS
T = 0... +70oC, voltages are referred to VSS unless otherwise specified:
I/O PORT PINS Symbol VIL V IH VHYS VOL VOH IL ISV RPU RPD Parameter Input low level voltage Input high level voltage Schmidt trigger voltage hysteresis * Output low level voltage for Standard I/O port pins Output high level voltage Input leakage current Static current consumption Pull-up equivalent resistor Pull-down equivalent resistor (PB6) Output high to low level fall time for Standard I/O port pins Output high to low level fall time for high sink I/O port pins Output L-H rise time External interrupt pulse time Cl=50pF I=-5mA I=-2mA I=5mA I=2mA VSS VIH V IN < VIL VIN > VIH V IN < VIL Cl=50pF 20 60 20 60 14.8 TBD 14.4 1 40 120 40 120 25 TBD 25 VDD-1.3 VDD-0.4 1 200 80 240 80 240 45.6 TBD 45.9 t CPU ns A K K 0.7xV DD 400 1.3 0.4 V Conditions Min Typ Max 0.3xVDD Unit V mV
tOHL tOLH tITEXT
* Note: Hysteresis voltage between Schmitt trigger switching levels. Based on characterisation results, not tested.
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7.3 SUPPLY, RESET AND CLOCK CHARACTERISTICS (T = 0 to +70 oC, VDD - VSS = 6 V unless otherwise specified.
LOW VOLTAG E DETECTOR AND SUPERVISOR (LVDS) Symbol VIT+ VITVhys Parameter Reset release threshold (VDD rising) Reset generation threshold (VDD falling) Hysteresis VIT+ - VITConditions Min Typ 3.7 3.2 500* Max Unit V V mV
Note *: the Vhys hysteresis is constant.
RESET SEQUENCE MANAGER (RSM) Symbol R ON tPULSE Parameter Reset weak pull-up resistance External RESET pin Pulse time Conditions VIN > VIH VIN < VIL Min 20 60 20 Typ 40 120 Max 80 240 Unit k s
7.4 TIMING CHARACTERISTICS (Operating conditions TA = 0 to +70C unless otherwise specified)
Symbol tINST t IRT Parameter Instruction time Interrupt reaction time tIRT = tINST + 10* Conditi ons Min 2 10 Typ Max 12 22 Unit tCPU tCPU
* tINST is the number of tCPU to finish the current instruction execution.
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7.5 MEMORY CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 7.5.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode 1) Conditi ons HALT mode (or RESET) Min 1.6 Typ Max Unit V
7.5.2 FLASH Program Memory
Symbol tprog tret N RW Parameter Programming time for 1~16 bytes Programming time for 4 KBytes Data retention 4) Write erase cycles
4) 2)
Conditions TA =+25C TA =+25C TA =+55C 3) TA =+25C
Min
Typ 8 2.1
Max 25 6.4
Unit ms sec years cycles
20 100
Notes: 1. Minimum V DD supply voltage without losing data stored in RAM (in in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production.
7.6 LCD ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltage Referenced to VSS) Note: Electrical simulations on design database and product characterization will be done over [0 to +70C] temperature range.
Symbol VLCD IVDDP_i - IVSSP_i Ratings Max. Display Voltage Note: VLCD=VDD Total current into VDDP_i/VSSP_i Value 6.6 80/80 Unit V mA
(T = 0... +70 oC, VDD - VSS = 6 V unless otherwise specified)
LCD DRIVER Symbol fFR VOS VCOH VCOL VSOH VSOL VLCD C LOAD Parameter Condit ions fRCINT=7.16 MHz fOSC=8 MHz VLCD=VDD no load I=100A, VLCD=5V I=50A, VLCD=5V I=50A, VLCD=5V I=100A, VLCD=5V VLCD = VDD Min (2) 53 61 4.5 0.5 4.5 4.5 0.5 6.6 50 Typ(2) Max(2) 437 488 50 Unit Hz Hz mV V V V V V pF
Frame frequency DC Offset Voltage (1) COM High Level, Output Voltage COM Low Level, Output Voltage SEG High Level, Output Voltage SEG Low Level, Output Voltage Display Voltage LCD dot Load
Notes:
1) The DC offset voltage refers to all segment and common outputs. It is the interface between the measured voltage value and nominal value for every voltage level. Ri of voltage meter must be greater than or equal to 10MW. 2) Target value to be confirmed after product characterisation.
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7.7 SMARTCARD SUPPLY SUPERVISOR ELECTRICAL CHARACTERISTICS (TA = 0... +70oC, VDD - VSS = 6 V unless otherwise specified)
SMARTCARD SUPPLY SUPERVISOR Symbol Parameter Condit ions Min SSS DRIVER bit SSR=1 : 5V regulator output (for IEC7816-3 Class A Cards) VSC_PWR SmartCard Power Supply Voltage VDD-VSS>V SC_PWR+0.5V 4.5 VDD-VSS = 5.5V, SmartCard Supply Current VSC_PWR=4.5V ISC VDD-VSS = 6 V, VSC_PWR=4.8V Voltage Drop Threshold on Current VOVLD VDD-VSS = 6V, RVDD=0V Overload SSS DRIVER bit SSR=0 : 3V regulator output (for IEC7816-3 Class B Cards) VSC_PWR SmartCard Power Supply Voltage 2.7 VDD-VSS = 3.5V ISC VDD-VSS = 4.5V SmartCard Supply Current VDD-VSS = 5V Voltage Drop Threshold on Current VOVLD VDD-VSS = 6V, RVDD=0V Overload Toff VSC Turn off Time C LOADmax=20uF Ton VSC Turn on Time C LOADmax=20uF Smart Card I/O Pins VIL Input Low Level Voltage V IH Input High Level Voltage 0.7VSCPW R V OL Output Low Level Voltage I=-2.6mA VOH Output High Level Voltage I=2.6mA TBD IL Input Leakage Current VSS3.00
3.3 TBD 30 50
V mA mA V
2.4 200 200 30 30 0.3VSCP WR TBD 10 250 -
us us V V V V A K ns ns
Figure 40. ISC Load with 5V Regulator Output (for IEC7816-3 Class A Cards)
VSC_PWR
5.5 5.0
VDD=6.5V
4.5
VDD=5.5V
4.0 3.5 10 20 30 40 50 60 70
VDD=6V
Load ISC [mA]
IEC7816-3 Spec
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Figure 41. ISC Load with 3V Regulator Output (for IEC7816-3 Class B Cards)
V SC_PWR
3.5 3.0 2.5
VDD=5V
VDD=4.5V
2.0 Load ISC 10 20 30 40 50 60 70 [mA]
IEC7816-3 Spec
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8 DEVICE CONFIGURATION
Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (ROM). FLASH devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. 8.1 OPTION BYTE The option byte allows the hardware configuration of the microcontroller to be selected. The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). Bit 7:1 = Reserved, must always be 1. Bit 0 = FMP Full memory protection. This option bit enables or disables external access to the internal program memory (read-out protection). Clearing this bit causes the erasing (to 00h) of the whole memory (including the option byte). 0: Program memory not read-out protected 1: Program memory read-out protected
OPTION BYTE 7 Reserved Default Value 1 1 1 1 1 1 1 0 FMP 0
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9 GENERAL INFORMATION
9.1 PACKAGE MECHANICAL DATA Figure 42. 64-Pin Thin Quad Flat Package
Dim A A1 A2 B C D D1 D3 E E1 E3 e K L1 L L L1 K N
mm Min 0.05 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
1.35 1.40 1.45 0.053 0.055 0.057 0.30 0.37 0.45 0.012 0.015 0.018 0.09 16.00 14.00 12.00 16.00 14.00 12.00 0.80 0 3.5 1.00 64 ND 16 7 0.039 NE 16 0.20 0.004 0.630 0.551 0.472 0.630 0.551 0.472 0.031 0.008
0.45 0.60 0.75 0.018 0.024 0.030 Number of Pins
Figure 43. 64-Pin Epoxy Thin Quad Flat Package
P Dim A L1 L n G A1 B E E1 e G L B L1 n P A1 A ETQFP 64 N 0.50 1.10 0.35 1.10 Number of Pins 64 (4x16) e mm Min Typ Max 2.40 0.60 Min inches Typ Max 0.095 0.024
0.25 0.38 0.50 0.010 0.015 0.020 15.80 16.00 16.20 0.622 0.630 0.638 12.20 12.35 12.50 0.480 0.486 0.492 0.80 13.10 0.020 0.043 0.013 0.043 0.031 0.515
Note: " QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES (ESO/EDIL/EQFP) IS NOT AUTHORIZED It is expressly specified that qualification and/or volume production of devices using the package E.... in any applications is not authorized. Usage in any application is strictly restricted to development purpose. Similar devices are available in plastic package mechanically compatible to the epoxy package for qualification and volume production."
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PACKAGE MECHANICAL DATA (Cont'd) Figure 44. Recommended Reflow Oven Profile (MID JEDEC) 250 200 Temp. [C] 150 100 50 0 100 9.2 ADAPTOR / SOCKET PROPOSAL To solder the (E)TQFP64 package or to plug the emulator probe, the application board should provide the footprint described in Figure 45. This footprint allows the following connexion configurations:
s s ramp up 2C/sec for 50sec 150 sec above 183C 90 se c at 125C Tmax=220 +/-5C for 25 sec
ramp do wn natural 2C/sec max
Time [sec] 200 300 400
Direct (E)TQFP64 soldering YAMAICHI IC149-064-008-S5* socket soldering to plug either the emulator probe or an adaptator board with an (E)TQFP64 clamshell socket delivered with the emulator. * Not compatible with (E)TQFP64 package.
Figure 45. (E)TQFP64 device and emulation probe compatible footprint
SK E E1 E3
B E Dim Min Typ Max Min Typ Max mm inches
0.35 0.45 0.50 0.014 0.018 0.020 20.80 14.00 0.819 0.551
e
E1
E3 11.90 12.00 12.10 0.468 0.472 0.476
E1
SK E
E3
B
6 2 &. ( 7
e SK*
0.75 0.80 0.85 0.029 0.031 0.033 26 1.023 Number of Pins
DETAIL
N
64 (4x16)
* SK: Plastic socket overall dimensions.
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9.3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: http//mcu.st.com. Third Party Tools s ACTUM s BP s COSMIC s CMX s DATA I/O s HITEX s HIWARE s ISYSTEM s KANDA s LEAP Tools from these manufacturers include C compliers, emulators and gang programmers. Table 15. STMicroelectronic Tool Features
In-Circuit Emulation ST7 Development Kit Programming Capabili ty1) Software Included ST7 CD ROM with: - ST7 Assembly toolchain - STVD7 and WGDB7 powerful Source Level Debugger for Win 3.1, Win 95 and NT - C compiler demo versions - ST Realizer for Win 3.1 and Win 95. - Windows Programming Tools for Win 3.1, Win 95 and NT Yes. (Same features as HDS2 emulator but without Yes (DIP packages only) logic analyzer) Yes, powerful emulation features including trace/ logic analyzer No
STMicroelectronics Tools Three types of development tool are offered by ST, all of them connect to a PC via a parallel (LPT) port: see Table 15 and Table 16 for more details.
ST7 HDS2 Emulator
ST7 Programming Board No
Yes (All packages)
Table 16. Dedicated STMicroelectronics Development Tools
Suppo rted Products ST72411, ST72C411 ST7 HDS2 Emulator ST7MDT7-EMU2B ST7 Programming Board ST7MDT7-EPB2/EU ST7MDT7-EPB2/US ST7MDT7-EPB2/UK
Note: 1. In-Situ Programming (ISP) interface for FLASH devices.
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9.4 ST7 APPLICATION NOTES
Identification PROGRAMMING AND TOOLS AN985 AN986 AN987 AN988 AN989 AN1039 AN1064 AN1179 EXAMPLE DRIVERS AN969 AN970 AN971 AN972 AN973 AN974 AN976 AN979 AN980 AN1017 AN1041 AN1042 AN1044 AN1045 AN1047 AN1048 AN1048 AN982 AN1014 AN1070 AN910 AN990 AN1181 AN1086 ST7 SCI communication between the ST7 and a PC ST7 SPI communication between the ST7 and E PROM ST7 I C communication between the ST7 and E PROM ST7 software SPI master communication SCI software communication with a PC using ST72251 16-bit timer Real time clock with the ST7 timer output compare Driving a buzzer using the ST7 PWM function Driving an analog keyboard with the ST7 ADC ST7 keypad decoding techniques, implementing wake-up on keystroke Using the ST7 USB microcontroller Using ST7 PWM signal to generate analog output (sinusoid) ST7 routine for I C slave mode management Multiple interrupt sources management for ST7 MCUs ST7 software implementation of I C bus master Managing reception errors with the ST7 SCI peripheral ST7 software LCD driver ST7 timer PWM duty cycle switch for true 0% or 100% duty cycle Using ceramic resonators with the ST7 How to minimize the ST7 power consumption ST7 checksum selfchecking capability ST7 and ST9 performance benchmarking ST7 benefits versus industry standard Electrostatic discharge sensitivity measurement ST7 / ST10U435 CAN-Do solutions for car multiplexing Executing code in ST7 RAM Using the ST7 indirect addressing mode ST7 in-circuit programming Starting with ST7 assembly tool chain Starting with ST7 Hiware C ST7 math utility routines Writing optimized hiware C language for ST7 Programming ST7 Flash Microcontrollers in Remote ISP Mode (In-Situ Programming) Description
PRODUCT OPTIMIZATION
PRODUCT EVALUATION
APPLICATION EXAMPLES
9.5 TO GET MORE INFORMATION To get the latest information on this product please use the ST web server. http://mcu.st.com/
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10 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision 1.3 Main changes Changed section 3.1 on page 15 (LVDS, OPSD and PSS behaviour If OSC_SEL tied to VDD) Added Figure 13 1.4 Added Electrical Characteristics section 7 on page 56. Added Figure 38 on page 47 to SSS chapter 25-Jan-00 Date 11-Nov-99
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10.1 DEVICE CONFIGURATION AND ORDERING INFORMATION 10.1.1 Transfer Of Customer Code Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Figure 46. ROM Factory Coded Device Types
TEMP. DEVICE PACKAGE RANGE / XXX Code name (defined by STMicroelectronics) 1= standard 0 to +70 C T= TQFP ST72411
Figure 47. OTP User Programmable Device Types
TEMP. DEVICE PACKAGE RANGE
1= standard 0 to +70 C T= TQFP ST72C411
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2000 STMicroelectronics - All Rights Reserved. Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http:// www.st.com
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